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SE1020W
1.25 Gb/s Transimpedance Amplifier Product Preview
Applications
Gigabit-Ethernet systems, test equipment and modules OC-24 fibre optic modules and line termination Fibre Channel optical systems
Product Description
SiGe Semiconductor offers a portfolio of optical networking ICs for use in high-performance optical transmitter and receiver functions, from 155 Mb/s up to 12.5 Gb/s. SiGe Semiconductor's SE1020W is a fully integrated, silicon bipolar transimpedance amplifier; providing wideband, low noise preamplification of signal current from a photodetector. It features differential outputs and incorporates an automatic gain control mechanism to increase dynamic range, allowing input signals up to 2.6 mA peak. A decoupling capacitor on the supply is the only external circuitry required. A system block diagram is shown after the functional description, on page 3.
Features
Single +3.3 V power supply Power dissipation = 110 mW (typ) Input noise current = 180 nA rms when used with a 0.7 pF detector Transimpedance gain = 4.0 k into a 50 load (differential) On-chip automatic gain control gives input current overload of 2.6 mA pk and max output voltage swing of 300 mV pk-pk Differential 50 outputs Bandwidth (-3 dB) = 1.2 GHz Wide data rate range = 50 Mb/s to 1.25 Gb/s Constant photodiode reverse bias voltage = 1.5 V (anode to input, cathode to VCC) Minimal external components, supply decoupling only Operating junction temperature range = -40C to +125C
Ordering Information
Type SE1020W Package Bare Die Remark None
Functional Block Diagram
SE1020 TzAmp 1.25 Gb/s
Automatic Gain Control
Integrator
Rectifier
VCC or +ve supply
Input Current TZ_IN
Rf
50
Tz Amp
Output Driver
OUTP OUTN
50
Bandgap Reference
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Bondpad Diagram
VCC
1
10
VCC
Top View
9 TZ_IN 2 8 OUTN OUTP
3 VEE2
4 VEE1
5 VEE1
6 VEE1
7 VCC
Bondpad Description
Pad No. 1 2 3 4 5 6 7 8 9 10 Name VCC TZ_IN VEE2 VEE1 VEE1 VEE1 VCC OUTN OUTP VCC Description Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one pad needs to be bonded. Input pad (connect to photodetector anode). Negative supply (0V) - Note this is separate ground for the input stage, which is AC coupled on chip. There is no DC current through this pad. Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad needs to be bonded. Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad needs to be bonded. Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad needs to be bonded. Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one pad needs to be bonded. Negative differential voltage output. Positive differential voltage output. Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one pad needs to be bonded.
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Functional Description
Amplifier front-end The transimpedance front-end amplifies an input current from a photodetector, at pin TZ_IN, to produce an output voltage with the feedback resistor Rf determining the level of amplification (see the functional block diagram on page 1). An automatic gain control loop varies this resistor, to ensure that the output from the front-end does not saturate the output driver stage that follows. This gain control allows input signals of up to 2.6 mA peak. The input pin TZ_IN is biased at 1.5 V below the supply voltage VCC, allowing a photodetector to have a constant reverse bias by connecting the cathode to 3.3 V. This enables full single rail operation. The front-end stage has its own supply ground connection (VEE2) to achieve optimum noise performance and maintain integrity of the highspeed signal path. The front-end shares the VCC
(+3.3 V) connection with the remainder of the circuitry, which has a separate ground (VEE1). Output driver stage The output driver acts as a buffer stage, capable of swinging up to 300 mVpk-pk differential into a 100 load. The small output swings allow ease of use with low voltage post amplifiers (e.g. 3.3 V parts). Increasing optical input level gives a positive-going output signal on the OUTP pin. Automatic Gain Control (AGC) The AGC circuit monitors the voltages from the output driver and compares them to an internal reference level produced via the on-chip bandgap reference circuit. When this level is exceeded, the gain of the front-end is reduced by controlling the feedback resistor Rf. A long time-constant integrator is used within the control loop of the AGC with a typical low frequency cut-off of 10 kHz.
System Block Diagram
Receiver Module AGC Amplifier Clock Clock & Data Recovery Data LOS 2 SE1230 2
1.25 GHz
2
1.25 Gb/s
2
SE1020W
TZ Amplifier
PIN
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Electrical Specifications
Absolute Maximum Ratings These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of the device. Avoid operating the device outside the recommended operating conditions defined below. Symbol VCC VIO IIO IIO VESD VESD Tstg Parameter Supply Voltage Voltage at any input or output Current sourced into any input or output except TZ_IN Current sourced into pin TZ_IN Electrostatic Discharge (100 pF, 1.5 k) except TZ_IN Electrostatic Discharge (100 pF, 1.5 k) pin TZ_IN Storage Temperature Min -0.7 -0.5 -20 -5 -2 -0.25 -65 Max 6.0 VCC+0.5 +20 +5 2 0.25 150 Unit V V mA mA kV kV C
Recommended Operating Conditions Symbol VCC Tj Parameter Supply Voltage Operating Junction Temperature Min 3.1 -40 Typ 3.3 Max 3.5 125 Unit V C
DC Electrical Characteristics Symbol ICC max ICC zero lagc Vin Vout Rout Parameter Supply Current (max input current) Supply Current (zero input current) AGC Threshold Input Bias Voltage Output Bias Voltage Output Resistance 35 24 VCC-1.57 VCC-1.52 VCC-0.15 50 65 VCC-1.47 Min Typ 41 33 Max 65 52 Unit mA mA A pk-pk V V
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AC Electrical Characteristics Symbol BW (3dB) Tz Dri Voutmax Flf lOL Pol Nrms Parameter Small Signal Bandwidth at -3dB point Differential Transimpedance (50 on each output, f = 100 MHz) Input Data Rate Maximum Differential Output Voltage Low Frequency Cut-off Input Current before overload (1.25 Gb/s NRZ data) Optical Overload Input Noise Current (in 1 GHz) 2600 +3.3 180 255 10 Min 0.95 2.9 50 Typ 1.2 4.0 5.4 1250 300 20 Max Unit GHz k Mb/s mV pk-pk kHz A pk-pk dBm nA rms
DC and AC electrical characteristics are specified under the following conditions: Supply Voltage (VCC) ................................... 3.1 V to 3.5 V Junction Temperature (Tj) ............................. -40C to 125C Load Resistor (RL) ......................................... 50 AC coupled via 220 nF, for each output Photodetector Capacitance (Cd) ................... 0.7 pF Input bond wire inductance............................ 1 nH Photodetector responsivity ............................ 0.6 A/W Transimpedance (Tz) measured with 4 A mean photocurrent
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Bondpad Configuration
The diagram below shows the bondpad configuration of the SE1020W Transimpedance Amplifier: Note that the diagram is not to scale. Bondpad openings are 82 m x 82 m. There are three VCC and three VEE1 pads for ease of wire bonding - the VCC and VEE1 pads respectively are connected on-chip and only one pad of each type is required to be bonded out.
1.25 mm
VCC
1
10
VCC
Top View
9 TZ_IN 2 8 OUTN OUTP
0.925 mm
3 VEE2
4 VEE1
5 VEE1
6 VEE1
7 VCC
Applications Information
For optimum performance it is recommended that the device be configured as in the circuit shown in the diagram below. Note that all VCC pads (1, 7, 10) are connected on-chip, as are the VEE1 pads (4, 5, 6),.and only one pad of each type is required to be bonded out. However, in order to minimize inductance for optimum high speed performance, it is recommended that all power pads are wire bonded. The VEE2 pad is not connected on chip to VEE1 and must be bonded out separately.
+3.3 V
PIN or APD Bias 1 nF min
1
7
10 9 8
1 nF min
VCC
2
PIN or APD
TZ Amplifier SE1020W
TZ_IN VEE2
3 4
OUTP OUTN
VEE1
5 6
To 50 loads, AC coupled
0V
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1.25 Gb/s Transimpedance Amplifier Product Preview
http://www.sige.com Headquarters: Canada
Phone: +1 613 820 9244 Fax: +1 613 820 4933
2680 Queensview Drive Ottawa ON K2B 8J9 Canada
sales@sige.com
U.S.A. 1150 North First Street San Jose, CA USA 95112 Phone: +1 408 998 5060 Fax: +1 408 998 5062
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Product Preview The datasheet contains information from the product concept specification. SiGe Semiconductor reserves the right to change information at any time without notification. Preliminary The datasheet contains information from the design target specification. SiGe Semiconductor reserves the right to change information at any time without notification. Final The datasheet contains information from the final product specification. SiGe Semiconductor reserves the right to change information at any time without notification. Production testing may not include testing of all parameters. Information furnished is believed to be accurate and reliable and is provided on an "as is" basis. SiGe Semiconductor Inc. assumes no responsibility or liability for the direct or indirect consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license or indemnity is granted by implication or otherwise under any patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SiGe Semiconductor Inc. products are NOT authorized for use in implantation or life support applications or systems without express written approval from SiGe Semiconductor Inc. Copyright 2002 SiGe Semiconductor All Rights Reserved
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